module axi_sram_controller #(
  parameter DATA_WIDTH  = 8,
  parameter ADDR_WIDTH  = 16,
  parameter BANK_BITS   = 6,
  parameter NUM_SRAM = 64
)(
  input clk,
  input rst_n,

  // AXI Write Interface
  input [ADDR_WIDTH-1:0] awaddr,
  input awvalid,
  output reg awready,

  input [DATA_WIDTH-1:0] wdata,
  input wvalid,
  output reg wready,

  output reg [1:0] bresp,
  output reg bvalid,
  input bready,

  // SRAM Interface
  output reg [ADDR_WIDTH-BANK_BITS-1:0] sram_addr,
  output reg [DATA_WIDTH-1:0] sram_din,
  output reg [BANK_BITS-1:0] bank_sel,
  output reg [NUM_SRAM-1:0] sram_cs,   // One-hot片选信号
  output reg [NUM_SRAM-1:0] sram_wen // One-hot写使能
);

always @(posedge clk) begin
  if (!rst_n) begin
    awready <= 1'b0;
    sram_wen <= 1'b1;
    sram_cs <= 1'b0;
  end
  else begin
    if(awvalid)
    //从机准备好接受写入地址
    begin
      awready <= 1'b1;
      sram_addr <= awaddr[9:0];
      bank_sel <= awaddr[15:10];
      sram_wen <= 1'b0;
    end
    else if (bready && bvalid)
    begin
      sram_wen <= 1'b1;
      awready <= 1'b0;
    end
    else begin
      awready <= 1'b0;
    end
  end
  
end

always @(posedge clk) begin
  if (!rst_n) begin
    wready <= 1'b0;
  end
  else begin
    if (wvalid) begin
      wready <= 1'b1;
      sram_din <= wdata;
      sram_cs <= (1 << bank_sel);  // 生成One-hot片选
      sram_wen <= (1 << bank_sel); // 生成One-hot写使能
    end
    else begin
      wready <= 1'b0;
    end
  end
end

always @(posedge clk) begin
  if (!rst_n) begin
    bvalid <= 1'b0;
    bresp <= 2'b0;
  end
  else begin
    if (awready && awvalid && ~bvalid && wready && wvalid) begin
      bvalid <= 1'b1;
      bresp <= 2'b0;
    end
    else begin
      if (bready && bvalid) begin
        bvalid <= 1'b0;
      end
    end
  end
end



endmodule